74ac00, 74act00 ?quad 2-input nand gate ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 ja n uary 2008 74ac00, 74act00 quad 2-input nand gate features i cc reduced by 50% outputs source/sink 24ma act00 has ttl-compatible inputs general description the ac00/act00 contains four, 2-input nand gates. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. connection diagram pin description logic symbol ieee/iec order number package number package description 74ac00sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac00sj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac00mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac00pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74act00sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74act00sj m14d 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74act00mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act00pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pin names description a n , b n inputs o n outputs
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 2 74ac00, 74act00 ?quad 2-input nand gate absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5v to +7.0v i ik dc input diode current v i = ?.5v ?0ma v i = v cc + 0.5 +20ma v i dc input voltage ?.5v to v cc + 0.5v i ok dc output diode current v o = ?.5v ?0ma v o = v cc + 0.5v +20ma v o dc output voltage ?.5v to v cc + 0.5v i o dc output source or sink current ?0ma i cc or i gnd dc v cc or ground current per output pin ?0ma t stg storage temperature ?5? to +150? t j j unction temperature 140? symbol parameter rating v cc supply voltage ac 2.0v to 6.0v act 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ?0? to +85? ? v / ? t minimum input edge rate, ac devices: v in from 30% to 70% of v cc , v cc @ 3.3v, 4.5v, 5.5v 125mv/ns ? v / ? t minimum input edge rate, act devices: v in from 0.8v to 2.0v, v cc @ 4.5v, 5.5v 125mv/ns
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 3 74ac00, 74act00 ?quad 2-input nand gate dc electrical characteristics for ac notes: 1. all outputs loaded; thresholds on input associated with output under test. 2. maximum test duration 2.0ms, one output loaded at a time. 3. i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 2.1 2.1 v 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 0.9 0.9 v 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 i out = ?0? 2.99 2.9 2.9 v 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 v in = v il or v ih , i oh = ?2ma 2.56 2.46 4.5 v in = v il or v ih , i oh = ?4ma 3.86 3.76 5.5 v in = v il or v ih , i oh = ?4ma (1) 4.86 4.76 v ol maximum low level output voltage 3.0 i out = 50? 0.002 0.1 0.1 v 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 v in = v il or v ih , i ol = 12ma 0.36 0.44 4.5 v in = v il or v ih , i ol = 24ma 0.36 0.44 5.5 v in = v il or v ih , i ol = 24ma (1) 0.36 0.44 i in (3) maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i old minimum dynamic output current (2) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ?5 ma i cc (3) maximum quiescent supply current 5.5 v in = v cc or gnd 2.0 20.0 ?
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 4 74ac00, 74act00 ?quad 2-input nand gate dc electrical characteristics for act notes: 4. all outputs loaded; thresholds on input associated with output under test. 5. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units t yp. guaranteed limits v ih minimum high level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out = 0.1v or v cc ?0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 0.8 v oh minimum high level output voltage 4.5 i out = ?0? 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 4.5 v in = v il or v ih , i oh = ?4ma 3.86 3.76 5.5 v in = v il or v ih , i oh = ?4ma (4) 4.86 4.76 v ol maximum low level output voltage 4.5 i out = 50? 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 4.5 v in = v il or v ih , i ol = 24ma 0.36 0.44 5.5 v in = v il or v ih , i ol = 24ma (4) 0.36 0.44 i in maximum input leakage current 5.5 v i = v cc , gnd ?.1 ?.0 ? i cct maximum i cc /input 5.5 v i = v cc ?2.1v 0.6 1.5 ma i old minimum dynamic output current (5) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ?5 ma i cc maximum quiescent supply current 5.5 v in = v cc or gnd 2.0 20.0 ?
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 5 74ac00, 74act00 ?quad 2-input nand gate ac electrical characteristics for ac note: 6. voltage range 3.3 is 3.3v ?0.3v. voltage range 5.0 is 5.0v ?0.5v. ac electrical characteristics for act note: 7. voltage range 5.0 is 5.0v ?0.5v. capacitance symbol parameter v cc (v) (6) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. t plh propagation delay 3.3 2.0 7.0 9.5 2.0 10.0 ns 5.0 1.5 6.0 8.0 1.5 8.5 t phl propagation delay 3.3 1.5 5.5 8.0 1.0 8.5 ns 5.0 1.5 4.5 6.5 1.0 7.0 symbol parameter v cc (v) (7) t a = +25?, c l = 50pf t a = ?0? to +85?, c l = 50pf units min. typ. max. min. max. t plh propagation delay 5.0 1.5 5.5 9.0 1.0 9.5 ns t phl propagation delay 5.0 1.5 4.0 7.0 1.0 8.0 ns symbol parameter conditions typ. units c in input capacitance v cc = open 4.5 pf c pd po w er dissipation capacitance v cc = 5.0v 30.0 pf
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 6 74ac00, 74act00 ?quad 2-input nand gate physical dimensions figure 1. 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ land pattern recommendation notes: unless otherwise specified a) this package conforms to jedec ms-012, variation ab, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x145-14m e) drawing conforms to asme y14.5m-1994 f) drawing file name: m14arev13 pin one indicator 8 0 seating plane detail a scale: 20:1 gage plane 0.25 x45 1 0.10 c c b c a 7 m 14 b a 8 see detail a 5.60 0.65 1.70 1.27 8.75 8.50 7.62 6.00 4.00 3.80 (0.33) 1.27 0.51 0.35 1.75 max 1.50 1.25 0.25 0.10 0.25 0.19 (1.04) 0.90 0.50 0.36 r0.10 r0.10 0.50 0.25
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 7 74ac00, 74act00 ?quad 2-input nand gate physical dimensions (continued) figure 2. 14-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 8 74ac00, 74act00 ?quad 2-input nand gate physical dimensions (continued) figure 3. 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & botto m 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 9 74ac00, 74act00 ?quad 2-input nand gate physical dimensions (continued) figure 4. 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchild s worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductor s online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 14 8 7 1 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and tolerances per asme y14.5-1994 e) drawing file name: mkt-n14arev7 6.60 6.09 8.12 7.62 0.35 0.20 19.56 18.80 3.56 3.30 5.33 max 0.38 min 1.77 1.14 0.58 0.35 2.54 3.81 3.17 8.82 (1.74)
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac00, 74act00 rev. 1.4.1 10 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fps e-series gto i-lo intellimax isoplanar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 pow er247 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot -6 s upersot -8 syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchild s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information form first production ative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i32 74ac00, 74act00 ?quad 2-input nand gate
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